Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)

YosysHQ, updated 🕥 2023-03-20 08:12:39

Project IceStorm aims at documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files.

See http://bygone.clairexen.net/icestorm/ for more information.

Most of Project IceStorm is licensed under the ISC license:

Permission to use, copy, modify, and/or distribute this software for any

purpose with or without fee is hereby granted, provided that the above

copyright notice and this permission notice appear in all copies.

THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES

WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN

ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF

OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

Issues

Update BRAM NegClk info based on latest testing

opened on 2023-03-20 08:12:39 by gatecat

See https://github.com/YosysHQ/nextpnr/pull/1128

'initial begin' bit order vs assigning value on clock cycle

opened on 2022-11-12 11:17:34 by chrisruk

Hi,

I'm wondering if anyone might be able to help with a rather confusing issue I have, using yosys and an icestick FPGA board.

If I assign values to my BRAM within a clock cycle as in - https://github.com/chrisruk/matrixchip/blob/19553ce721103666b77f76f664355b2f1454d42b/src/matrix.v#L54

The output bitstream, which goes to an 8x8 SK9822 LED matrix to display a font, but the letter appears upside down.

But if I move the font assignments to an initial begin statement, it appears the correct way up on the LED matrix -

initial begin fonts[0] = 64'he0_60_6c_76_66_66_e6_00; // h fonts[1] = 64'h00_00_78_cc_fc_c0_78_00; // e fonts[2] = 64'h70_30_30_30_30_30_78_00; // l fonts[3] = 64'h00_00_78_cc_cc_cc_78_00; // o end

Just wondering if anyone has any idea how this could happen?

In a simulation with each version, both output clock and data bitstreams appear the same.

icepll enhancements

opened on 2022-10-01 05:09:51 by duskwuff

1) support PHASE_AND_DELAY + SHIFTREG feedback, which uses a 4x VCO multiplier behind the scenes

2) allow overriding clock constraints, just in case you like to live on the edge. my testing suggests that the 10 MHz F_pfd minimum is highly flexible, for example

Add support for iCE65 devices?

opened on 2022-08-19 01:37:30 by nonarkitten

It's rumoured these devices still exist even though Lattice seems to have gone out of their way to bury them. None of the development tools are available anymore, not from any site, so unless you were lucky to grab a copy then, you're out of luck. Supposedly, these are little different from the first iCE40 chips, just in a larger process that's 5V tolerant.