UVM 1.2 port to Python

tpoikela, updated 🕥 2023-03-29 17:39:04

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UVM library for Python

This is a port of SystemVerilog (SV) Universal Verification Methodology (UVM) 1.2 to Python and cocotb. Icarus Verilog (iverilog) and Verilator have been used for testing the code so far.

See documentation for more details: - uvm-python Documentation. - uvm-python User's Guide

SystemVerilog UVM is not currently supported by any open source/free tools. cocotb offers excellent solution to interact with any simulator (free/proprietary), so testbenches can be written in Python as well. uvm-python tries to offer an API similar to the original SV-UVM version. This means that many UVM verificaton skills and API knowledge are transferable from SV to Python very easily.

If you want to port a larger bulk of SV code to use uvm-python, you can try the script bin/sv2py.pl as the first step. It's a regex-based solution, and code will still require lots of manual edits to work.


The documentation is available on readthedocs.io in uvm-python HTML documentation.


You can install uvm-python as a normal Python package. It is recommended to use venv to create a virtual environment for Python prior to installation.

Install from PyPi using pip: shell python -m pip install uvm-python

or directly from source files (for the latest development version):

```shell git clone https://github.com/tpoikela/uvm-python.git cd uvm-python python -m pip install . # If venv is used

Or without venv, and no sudo:

python -m pip install --user . # Omit --user for global installation ```

See Makefile for working examples. You can also use Makefiles in test/examples/simple as a template for your project.

Running the examples and development

See test/examples/simple/Makefile for working examples. More features/examples will be added incrementally.

To run all tests: shell SIM=icarus make test # Use iverilog as a simulator

To run unit tests only: make test-unit # Does not require simulator

Minimal working example

uvm-python must be installed prior to running the example. Alternatively, you can create a symlink to the uvm source folder:

shell cd test/examples/minimal ln -s ../../../src/uvm uvm SIM=icarus make

You can find the source code for this example here. This example creates a test component, registers it with the UVM factory, and starts the test.

You can execute the example by running SIM=icarus make. Alternatively, you can run it with SIM=verilator make.


File: Makefile

TOPLEVEL_LANG ?= verilog VERILOG_SOURCES ?= new_dut.sv TOPLEVEL := new_dut MODULE ?= new_test include $(shell cocotb-config --makefiles)/Makefile.sim ```

The top-level module must match TOPLEVEL in Makefile:

verilog // File: new_dut.sv module new_dut(input clk, input rst, output[7:0] byte_out); assign byte_out = 8'hAB; endmodule: new_dut

The Python test file name must match MODULE in Makefile:


File: new_test.py

import cocotb from cocotb.triggers import Timer from uvm import *

@uvm_component_utils class NewTest(UVMTest):

async def run_phase(self, phase: UVMPhase):
    await Timer(100, "NS")
    uvm_info("NEW_TEST", "Test passed, all OK", UVM_MEDIUM)

@cocotb.test() async def test_dut(dut): await run_test('NewTest') ```

Current status

Testbenches can already be written with all the typical UVM components. UVM Phasing is in place, and working. Stimulus can be generated using (even hierarchical) sequences. Register layer supports already read/write to registers (via frontdoor), and to memories (frontdoor and backdoor). TLM 1.0 is implemented, put/get/analysis interfaces are done, and master/slave interfaces work. Initial implementation of TLM2.0 has also been added. The table below summarizes the status:

| Feature | Status | | --------- | ------ | | TLM1.0 | Done | | TLM2.0 | Done | | Components | Done | | Phases | Done | | Objections | Test and env-level objections work | | Sequences | Partially done, hier sequences work | | Registers | Reg/mem access working, built-in sequences partially done |

Please try it out, and let me know if something you require should be added, or even better, add it yourself, test it and create a pull request!

HDL Simulators

Tested with Icarus Verilog (iverilog v13.0 (devel)) and verilator (v5.008). The exact commit for iverilog can be found from ci/install_iverilog.sh.

Icarus Verilog and verilator are free simulators, which can be used with cocotb. uvm-python uses cocotb to interface with these simulators. Memory backdoor access has issues with packed multi-dimensional arrays in verilator. Also, some other examples are not working with verilator yet.

Proprietary simulators that work with cocotb should work with uvm-python as well, but haven't been tested.

Related projects


Latest version of cocotb Verilator will always issue error %Error-TIMESCALEMOD.

opened on 2021-03-14 15:20:08 by jg-fossh

The latest uvm-python depends on cocotb 1.5.0.rc2 which seems to have issues with verilator.

Even trying to set a combination of dependencies that could work seems to hang the simulation process, might be caused by changes in cocotb-bus or cocotb.

Correct way to clean up UVM objects

opened on 2021-02-16 21:29:04 by sjalloq

I've been using the register model I created and having now added more tests to a single file, I noticed I'm getting warnings that more than one uvm_reg_block have been instanced with the same name.

Am I supposed to be cleaning up each test somehow? Is there a particular helper method I should call?


registers/vertical_reuse blk-level simulation fails with ghdl/VHDL DUT

opened on 2020-12-20 11:11:06 by tpoikela

When running the above-mentioned example, uvm_fatal is thrown. Looks like APB monitor does not register any items during simulation.

Commands to reproduce the issue: cd test/examples/simple/registers/vertical_reuse SIM=ghdl make TOPLEVEL_LANG=vhdl IMG=BLK SIMARGS="-- +UVM_TESTNAME=blk_R_test" SIM_BUILD=sim_build_blk

Expected result: Test passes, and does not throw uvm_fatal.

Tuomas Poikela
GitHub Repository