The new home of the cocotb project's pre-packaged testbenching tools and reusable bus interfaces.
There is a current issue & PR raised relating to Avalon MM burst read/writes - #44.
After implementing these changes the Avalon Memory Model presents a scheduler error - "Write to object {} was scheduled during a read-only sync phase.", similar to that in #8.
The issue is with 337 async def _waitrequest(self):
both lines 344 and 349 can cause the above error.
It can be fixed similarly by adding await ReadWrite()
.
This makes the AvalonSTPkts monitor work with readyLatency in my code. Some more testing is probably wise.
If readyLatency is greater than zero only valid is checked to see if it is a valid cycle. A test is added to check if valid is asserted in an non ready cycle.
The _signals
/_optional_signals
definitions in amba.py
doesn't seem to conform with the specification. This PR corrects the _signals
and _optional_signals
definition according to the AMBA AXI and ACE Protocol Specification chapter A9.3.
Additionally, I added missing type annotations.
All test_axi4
tests fail for me. However, they also fail for me without the changes and are probably due to #33. Though, the example test_axi_lite_slave
passes.
I'm instantiating an AXI4LiteMaster in my testbench.
With the default behaviour in cocotb_bus 0.2.1 installed from pypi the following line fails:
https://github.com/cocotb/cocotb-bus/blob/2c846dca8d3293b7676c70dd51dbc9c7f51029f0/src/cocotb_bus/drivers/amba.py#L67
with AttributeError: 'NoneType' object has no attribute 'setimmediatevalue'
I traced the cause to this function:
https://github.com/cocotb/cocotb-bus/blob/2c846dca8d3293b7676c70dd51dbc9c7f51029f0/src/cocotb_bus/bus.py#L78-L82
When first called, obj
doesn't yet have the attributes (e.g. axil_AWVALID
) populated. The for loop will iterate through the dir
, but not find the signal we are looking for and the function will return None
as the handle.
I noticed that hasattr
and getattr
are not case sensitive for me. So my current workaround for this is to (counterintuitively) set case_insensitive=False
in the call to BusDriver.__init__
so this code doesn't get called.
https://github.com/cocotb/cocotb-bus/blob/2c846dca8d3293b7676c70dd51dbc9c7f51029f0/src/cocotb_bus/drivers/amba.py#L64
This PR adds a reset of the internal variables of AvalonSTPkts monitor. It prevents the Duplicate start-of-packet received ...
error when reset occurs in the middle of a transaction.
I use cocotb 1.6.2 to test the Bus.driver()
module dut(
input [7:0] data_in_data0,
input [7:0] data_in_data1,
output logic [7:0] data_out_data0,
output logic [7:0] data_out_data1
);
always_comb begin
data_out_data0=data_in_data1;
data_out_data1=data_in_data0;
end
endmodule
`class dataPkg(object): def init(self,data0,data1) -> None: self.data0=data0 self.data1=data1
@cocotb.test() async def testDemo(dut): dataIn=Bus(dut,"data_in",["data0","data1"]) await Timer(1,'ms') dataIn.drive(dataPkg(5,6)) await Timer(1,'ms')`
the data_in_data0 and data_in_data1 are not assigned by 5 and 6.the Bus.drive() not work
Install this release from PyPi with
python3 -m pip install cocotb-bus == 0.2.1
Changes: - Remove setuptools_scm as a dependency (#40) [Kaleb Barrett]
Full Changelog: https://github.com/cocotb/cocotb-bus/compare/v0.2.0...v0.2.1
Install this release from PyPi with
python3 -m pip install cocotb-bus == 0.2.0
Changes: - Improve compatibility with cocotb 1.6 - AXI: Enable case insensitive matching (#19, #29) [Aaron Holtzman, c-93] - Avalon: Don't sample in the postponed region (#26) [Greg Taylor] - Move lock methods to base class by (#23) [Todd Strader]
Full Changelog: https://github.com/cocotb/cocotb-bus/compare/v0.1.1...v0.2.0
testbench bus interface hdl verilog vhdl cocotb